The invention relates to a method for trench etching, in particular a method for anisotropic deep trench (DT) etching in an Si substrate by plasma dry etching, such as reactive ion etching (RIE), magnetically enhanced RIE or inductively coupled plasma etching (ICP), and sidewall passivation of the etched trenches in the Si substrate, the Si substrate being provided with an etching mask before the beginning of the etching operation.
Trench structures of this type are used in semiconductor structures, in particular in memory cells, in order to produce capacitances as storage medium. The etching operation is carried out for example in a dry etching installation with an inductively coupled plasma for activating the etching gases. Halogen-containing gases such as SF6, CF4, CHF3, C12, HBr, etc. are generally used as etching gases. A reactive ion etching method (RIE) of this type makes it possible to achieve etching depths of up to 50 xcexcm. The Internet publication by IMSAS, University of Bremen, entitled xe2x80x9cVolumen-Mikromechanikxe2x80x9d [xe2x80x9cBulk micromachiningxe2x80x9d], author: Feld, Udo, (http://www.imsas.uni-bremen.de), dated Jun. 9, 1998, describes an etching method which makes it possible to achieve such and larger etching depths using a so-called advanced silicon etch method. However, this method is suitable specifically for producing deep silicon structures for micromachining and has a high selectivity with respect to positive photoresist and also with respect to oxide masks. Possibilities for simultaneous sidewall passivation are not specified here, however.
The document xe2x80x9cEEP-Vol. 19-1, Advances in electronic packaging, 1997, Volume 1, ASME 1997, describes a device which is suitable for etching deep trenches and serves for reactive ion etching (RIE), particularly high etching rates being achieved using an inductively coupled plasma (ICP). In particular, a so-called xe2x80x9cBosch technologyxe2x80x9d is described which can be used to achieve larger etching depths by comparison with the RIE and ICP methods. This method uses SF6 as etching gas, and a particularly high concentration of atomic fluorine can be produced by the said SF6 in the plasma. This method is characterized in that etching and deposition steps alternate with one another. During the deposition cycle, a polymer protective layer is built up on the perpendicular sidewalk of the trench, which layer is intended to prevent incipient etching of the sidewalls during the etching step. Etching depths as far as 100 xcexcm can be achieved with this method. However, this method is relatively complex and has the particular disadvantage that in the case of very small structure widths, during the deposition cycle, the mask opening is constricted to an excessively great extent by the polymer layer.
As already set forth, deep trench structures are used in the Si substrate in order to produce capacitances. As is known, however, the capacitance of a capacitor is dependent on the capacitor area. If the intention is to produce such capacitances with a sufficient capacitance in silicon structures, then a problem arises from the fact that, as structure sizes become ever smaller, it is necessary to etch ever deeper trenches into the silicon in order to achieve a comparable or else at least usable capacitance.
In the case of the deep trench etching methods that are customarily used, the trench is etched in its entire depth such that a sidewall passivation is continuously built up in the already etched region, in order to prevent etching into the sidewall of the trench. This is done by the selection of suitable recipe parameters. The sidewall passivation is produced by the SiBr4 which is produced during the Si etching and reacts with 02 in the plasma to form a non-volatile SiBrO, which is then deposited on the sidewalk as a loose layer (redeposit). However, there is no possibility for preventing the already produced sidewall passivation from being attacked while the etching process progresses, i.e. the already produced sidewall passivation is etched away or thinned for lack of sufficient selectivity of the etching gases used. It must therefore be ensured throughout the etching process that the sidewall passivation in the already etched region does not become too thin, or that so-called side pockets with the risk of a short circuit to adjacent structures are produced, or that a higher leakage rate is to be recorded.
In order to avoid this problem, it is possible, in principle, to use a suitable recipe to produce a significant reinforcement of the sidewall passivation. This involves the risk, however, of the sidewall passivation becoming too thick, that is to say of the trench opening being constricted to an excessively great extent, so that the further depth etching is then prevented or at least impeded.
Taking account of all these boundary conditions leads to a considerable restriction in the selection and optimization of the recipe parameters and the hardware.
In order to be able to etch deeper trenches, as already described, multistep etching methods have also been disclosed, the sidewall passivation for the uncovered silicon sidewalk in this case being built up during the etching process. In order in this case to prevent or to reduce incipient sidewall etching, the recipe parameters have to be adapted at the expense of the etching rate.
The invention is based on the object, then, of providing a method for depth etching which, with a low outlay, makes it possible to achieve a significantly larger etching depth at higher speed and which enables a further reduction of the structure widths without any difficulty.
According to the invention, the object of the invention is achieved, in the case of a method of the type mentioned in the introduction, by virtue of the fact that a deep trench (DT) etching step into the Si substrate as far as a predetermined etching depth is performed, in that the redeposit produced during the DT etching step is replaced by a protective layer for the sidewall passivation, and in that the sequence of these steps is repeated until the envisaged target depth of the trench is reached, a break-through being etched through the protective layer at the bottom of the trench before each further DT etching step.
The particular advantage of this method is to be seen in the fact that the separation of etching step and passivation step results in a particularly good sidewall protection which allows the use of significantly more aggressive etching parameters, which enables deeper etching trenches to be produced. The removal of the redeposit after each etching step means that the opening of the etching trench does not remain greatly restricted, but rather is repeatedly widened. This also improves the transporting of the reactive etching gases into the trench and thus has a positive influence on the etching rate.
The loose redeposit can be removed in a simple manner by a wet etching step.
The required protective layer is advantageously produced from a thermal oxide (Si02) by a thermal oxidation, as a result of which the sidewall roughness of the Si, which was produced as a result of plasma etching damage, is simultaneously annealed again.
Instead of the thermal oxide as protective layer, the latter can also be produced from a conformally deposited metal.
It furthermore suffices for the thickness of the protective layer to be 2-5 nm.
In an advantageous refinement of the invention, the break-through etching step is carried out in situ before the DT etching step.